Difference between revisions of "Virage0-1"
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(Fix mistakes and update) |
Stuckpixel (talk | contribs) |
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| Line 20: | Line 20: | ||
| 0x06 || 0x02 || tidWindow || Seems to be always 0x001A | | 0x06 || 0x02 || tidWindow || Seems to be always 0x001A | ||
|- | |- | ||
| − | | 0x08 || | + | | 0x08 || 0x2 * 0x1A || cc || Play-time (600 minutes = 0x0258) |
|- | |- | ||
| 0x3C || 0x02 || seq || CRC | | 0x3C || 0x02 || seq || CRC | ||
Latest revision as of 00:31, 16 October 2019
Virage0 and Virage1 are two 4K EEPROM banks located inside the SoC that can only be read in secure mode.
| Offset | Size | Description | Note |
|---|---|---|---|
| 0x00 | 0x01 | tsCrlVersion | Seems to be always 0x00 |
| 0x01 | 0x01 | caCrlVersion | Seems to be always 0x00 |
| 0x02 | 0x01 | cpCrlVersion | Seems to be always 0x01 |
| 0x03 | 0x01 | contentRlVersion | Seems to be always 0x00 |
| 0x04 | 0x02 | ticketRlVersion | Seems to be always 0x0000 |
| 0x06 | 0x02 | tidWindow | Seems to be always 0x001A |
| 0x08 | 0x2 * 0x1A | cc | Play-time (600 minutes = 0x0258) |
| 0x3C | 0x02 | seq | CRC |
| 0x3E | 0x02 | sum | CRC |